1. Field of the Invention
The present invention relates to a flat panel display device such as a liquid crystal display and a plasma display, and to a data processing method for video data supplied to the flat panel display device.
2. Description of Related Art
In accordance with an increase in sizes of flat-panel type display devices such as liquid crystal television sets, higher definition and smoother motion have been demanded. In order to satisfy those demands, video data of still wider band is required so that a clock speed of such device has been enhanced. However, in accordance with the increase in the clock speed and the increase in the size of the display device, an influence of power supplies and an influence of deterioration in ground impedance have been significant. Accordingly, there has been a concern over deterioration in EMI (Electromagnetic Interference).
First, an outline of a flat panel display device will be described. FIG. 1 is a block diagram for describing a flat panel display device. In FIG. 1, a flat panel display device 100 includes a timing controller 101, eight signal drivers 1 to 8 for driving signal lines, four scan drivers 104 to 107 for driving scanning lines, and a display panel 108 for displaying video data. The timing controller 101 inputs parallel data. The parallel data includes video data of red, green, and blue, and timing signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The timing controller 101 generates control signals for controlling the eight signal drivers 1 to 8 and the four scan drivers 104 to 107 based on the timing signals. Further, the timing controller 101 performs processing such as rearranging the video data, adjusting the timing, and converting the bit number in accordance with structures of the signal drivers 1 to 8.
Referring to the drawing, the timing controller 101 transmits a scan driver start pulse and a scan driver clock to each of the scan drivers 104 to 107 via a control line 102. The scan drivers 104 to 107 receives the scan driver start pulse and the scan driver clock and drives the scanning lines of the display panel 108. The timing controller 101 also transmits a signal driver start pulse and a signal driver clock to the signal drivers 1 to 8 via a control line 103, and transmits video data to the signal drivers 1 to 8 through eight data lines 11 to 18. For transferring video data between the timing controller 101 and each of the signal drivers 1 to 8, differential signals with small amplitudes based on LVDS (Low Voltage Differential Signaling) are used. The signal drivers 1 to 8 receives the signal driver start pulse, the signal-driver clock, and the video data and drive the signal lines of the display panel 108.
A structure including a single signal driver for a single display panel of the flat panel display device seems to be idealistic. However, for driving a large display panel by a single signal driver, the circuit scale of the signal driver becomes too large. This results in increasing the manufacturing cost. Further, wiring between the display panel and the signal driver becomes difficult due to the difference in their sizes. Because of theses reasons, usually, in a flat panel display devices of 10-inch class or more, a single display panel is driven by a plurality of signal drivers, as shown in FIG. 1. Similarly, a plurality of scan drivers are provided to a single display panel as well. FIG. 1 shows the flat panel display device 100 which transfers video data with a point-to-point architecture by using a plurality of data lines 11 to 18. Here, “point-to-point architecture” transfer indicates a transfer form where a data input (receiver) of a single driver is connected to one port of a data output (transmitter) built in a timing controller. However, there is also a flat panel display device which transfers video data with a multi-drop architecture by using a common data bus.
Normally, the timing for the signal driver to output a drive voltage to the display panel is every one horizontal period. However, recently, the number of a type of devices is increased, that output the drive voltage in plurality of times in one horizontal scanning period in order to improve the display characteristic. Further, in flat panel display device for some types of usage, the vertical direction and the horizontal direction are exchanged to each other.
There are various kinds of common names for the signal driver and the scan driver. In a field of liquid crystal displays, the signal driver is referred to as a source driver, and the scan driver is referred to as a gate driver, for example.
The signal drivers 1 to 8 shown in FIG. 1 will be described in details. FIG. 2 shows a block diagram for describing the configuration of the signal driver 1. Only the signal driver 1 shown in FIG. 1 will be described herein, however, the other signal drivers 2-8 also have similar circuit structures. In FIG. 2, the signal driver 1 includes an input receiver 110, a serial-parallel conversion circuit 111, an internal data bus 112, a data latch 113, a data latch 114, a D/A converter 115, and an output amplifier 116.
The input receiver 110 is a circuit which converts a signal level of receiving video data into a CMOS level that is used inside the signal driver 1, when the video data on the data line 11 is a differential signal such as LVDS.
The serial-parallel conversion circuit 111 is a circuit which converts, when video data transferred in a serial form is to be latched, the serial video data into video data of parallel mode of a certain number of bits (expressed as “one group” in this application) which is a unit of latch processing. The number of bits in one group does not necessarily be consistent with the number of bits of a processing unit inside the timing controller 101.
The internal data bus 112 is a bus which transfers the parallel-mode video data converted by the serial-parallel conversion circuit 111 to the data latch 113 by one group at a time, and it is a group of wirings in the same number of bits as that in one group.
The data latch 113 successively latches one group of video data that is converted into parallel mode by the serial-parallel conversion circuit 111, and stores the video data for the signal lines that are driven by the signal driver 1.
The data latch 114 stores, once by every horizontal period, the video data stored in the data latch 113 in order to keep a signal line drive voltage output for one horizontal period.
The D/A converter 115 selects gray-scale voltages for driving the display panel 108 based on the video data stored in the data latch 114. The output amplifier 116 is a circuit for converting impedance so as to drive the display panel 108 with low impedance, since the D/A converter 115 normally has high output impedance so that it is not possible to drive the display panel 108 directly.
As an example of a technique related to an improvement of EMI, there is an invention “DISPLAY DEVICE AND DRIVING METHOD OF THE SAME” that is disclosed in Japanese Laid-Open Patent Application JP-P2002-341820A (referred to as “patent document 1” in the following). This invention is designed to disperse peak currents generated when transferring video data from the data latch 113 to the data latch 114 shown in FIG. 2. The invention suppresses the maximum instantaneous current consumption of an active-matrix type display device. According to the patent document 1, data load instruction signals (signals for the signal electrodes to output voltages in accordance with video signals transferred to signal-side driving means) of the signal-side driving means for driving a display panel are controlled at different timings for each signal-side driving means.
As another example related to an improvement of the EMI, there is an invention “NOISE REDUCING CIRCUIT FOR SEMICONDUCTOR DEVICE” that is disclosed in Japanese Laid-Open Patent Application JP-P2003-8424A (referred to as “patent document 2” in the following). The technique disclosed in the patent document 2 is designed to overcome the issue that there is a large noise generated inside a semiconductor of a liquid crystal display data control circuit (timing controller) because an instantaneous excessive current flows concentratedly on a power supply line. A large noise that is generated because the instantaneous excessive current flows concentratedly on the power supply line in an output I/O buffer of the data control circuit (timing controller) is reduced. The technique of the patent document 2 is applied not to a point-to-point architecture flat panel display device as shown in FIG. 1 but to the multi-drop architecture flat panel display device using a common data bus. Here, “Multi-drop” type transfer indicates a transfer form where (receivers of) a plurality of drivers are connected to one port of a transmitter built in a timing controller. In the patent document 2, delay circuits are added to the output buffers of a semiconductor device that has N-numbers of outputs so as to generate phase differences for each output so as to suppress simultaneous inversion of each output from H to L or from L to H so as to suppress an excessive peak current.